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| 5.4 Compile |
Select the project in project directory window. Right-click the mouse, then click “build project” or click in shortcut toolbar to compile, console window will display the information generated during the build process, which is shown in figure 5.4.1.
Figure 5.4.1
If the compilation is successful, the file generated during the build process is stored in the “obj” file in the source code directory, which is shown in figure 5.4.2.
Figure 5.4.2
If you need to further configure the build process, select the project in
project directory window, right-click the mouse, then click “properties”. The
following are common configurations, and these are shown in figure
5.4.3.
Figure 5.4.3
Click the drop-down options of “C/C++ Build” in left side, then select “Settings”, and select “Target processor” under “Tool Settings” in right side. The property configuration page of RISC-V core chip is shown in figure
Figure 5.4.4
Target processor mainly sets the
target processor properties. Please refer to GCC document 3.18.38 RISC-V Options
for detailed
information.
(1) Architecture
instruction set architecture, RV32I is basic integer instruction set of
RISC-V.
(2) RVM
supports multiplication and division
expansion.
(3) RVA
supports atom
expansion.
(4) RVF single-precision
floating-point
expansion.
(5) RVD
double- precision floating-point
expansion.
(6) RVC
compressed instruction
expansion.
(7) RVXW
custom compressed instruction expansion,
supports
lbu,lhu,lbusp,lhusp,sb,sh,sbsp,shsp 16-bit compressed
instruction.
(8) Integer
ABI
integer binary interface of RISC-V application.
(9) Floating
point ABI floating-point binary
interface of RISC-V application.
(10)
Tuning:
the output to the processor optimized by the micro-architecture,
the default is rocket.
(11) Code
mode
-mcmodel=medlow: the
program and its static defined symbols must
be located in a
single-2GiB address range, and must be located between 2 GiB and
2 GiB of the absolute address. This is the default code model.
-mcmodel=medany: the
program and its static defined symbols can be located in any
single-2GiB address, and program can be connected statically
or
dynamically.
(12)
Small data limit puts
global and static variables which are smaller than n-byte into
a special field on some targets.
(13)
Align
-mstrict-align -mno-strict-align depends on whether the processor
supports unaligned memory access.
RISC-V compiler supports many ABIs, which depends on whether there are F and D expansion. ABI of RV32 is named as ilp32, ilp32f and ilp32d. ilp32 means that 32-bit int, long and pointer of C language, and optional suffix means how to transfer floating-point parameters; in ilp32, floating-point parameters are transferred in integer register; in ilp32f, single-precision floating-point parameters are transferred in floating-point register; in ilp32d, double- precision floating-point parameters also are transferred in floating-point register.
If you want to transfer floating-point parameters in floating-point register,
it needs the corresponding ISA to add F or D expansion. So to compile the RV32I
code (GCC option -march=rv32i), it must use ilp32 ABI (GCC option -mabi=ilp32).
Otherwise, the calling convention does not require that floating-point
instructions must use the floating-point register, so RV32IFD, ilp32, ilp32f and
ilp32d all are compatible.
The property configuration of ARM core chip is
shown in figure 5.4.5.
Figure 5.4.5
(1) ARM
family
sets chip core type, CH32F103 core is corte-m3 in above
figure.
(2) Architecture
sets instruction set architecture, CH32F103 architecture is
ARMV7-M.
Generally,
after setting the chip core, this can choose the
default.
(3) Instruction
set sets
chip operating mode, thumb or arm mode.
(4) Thumb
interwork generates code
instruction set that supports be called between ARM
and Thumb. If there is no this option, on the above v5 architecture,
these two instruction sets cannot be used reliably in one
program.
(5) Endianness
sest the big and small terminal, the default is small
terminal.
(6) unaligned
access sets whether to allow
unaligned access. Enable (or disable) the reading
and writing of 16-bit or 32-bit value from the unaligned 16-bit or 32-bit
address.
In default, unaligned access disables all the above ARMv6
versions,
all ARMv6-M and ARMv8-M Baseline architectures. For other architectures,
it is enabled. After setting the chip core type ,other options can choose
the default properties if you are not sure.
Click the drop-down options of “C/C++ Build” in left
side, then select “Settings”, and select “Optimization” under
“Tool Settings” in right side. The property configuration page is shown in
figure 5.4.6.
Figure 5.4.6
The property configuration page mainly configures optimized options of GCC, if you want to add other optimized options that can be written in “other optimization flags”. The meanings of commonly optimized options are:
-O0:
no optimization (default)
-O and
-O1: Use
optimizations that can reduce the size of the object file and
the
execution time without significantly increasing the compilation time.
When compiling large programs, it will significantly increase the memory
usage.
-O2:
Contain the -O1 optimization and adds optimizations that do not need
to
compromise on the size and execution speed of the object file. The
compiler
does not perform loop unrolling and function correlation. This option
will
increase the compilation time and the execution performance of the object
file.
-Os:
Specially optimize the size of the object file, and execute all the -O2
optimization
that do not increase the size of the object file. And perform the
optimization
that specifically reduces the size of the object
file.
-O3:
Turn on all -O2 optimization and add some parameters.
Click the drop-down options of “C/C++ Build” in left side, then select “Settings”, and select “GNU RISC-V Cross C Link->Miscellaneous” under “Tool Settings” in right side. The property configuration page is shown in figure 5.4.7.
Figure 5.4.7
Tick “Use wchprintf”, it will use simplified “printf” function to reduce the number of codes. Common types: %s , %c, %d, %f, %x, %o, etc. Common formats: %m.n d, %m.nf , %0m d, %-m d, etc.
Tick “Use wchprintfloat”, it will increase the function of printing floating-point numbers. To compare with the “Use float with nano printf” provided by the standard library, the number of codes can be significantly reduced.
Click the drop-down options of “C/C++ Build” in left side, then select
“Settings”, and select “Build Steps” in right
side. The property configuration page is shown in figure 5.4.8.
Figure 5.4.8
In the red box can add instructions to be executed after compilation.
eg:
"${eclipse_home}\toolchain\RISC-V Embedded
GCC\bin\riscv-none-embed-objcopy"
-O
ihex"${ProjName}.elf" "文件存放路径\\${ProjName}.hex"
Used to
set the location of the generated hex file
"${eclipse_home}\toolchain\RISC-V Embedded
GCC\bin\riscv-none-embed-objcopy"
-O binary
"${ProjName}.elf""文件存放路径\\${ProjName}.bin"
Used
to set the location of the generated bin file
Click the drop-down options of “C/C++ Build” in left side, then select “Settings”, and select “Warnings” under “Tool Settings” in right side. The property configuration page is shown in figure 5.4.9.
Figure 5.4.9
Click the drop-down options of “C/C++ Build” in left side, then select “Settings”, and select “Miscellaneous” under “GNU RISC-V Cross C Linker” under “Tool Settings” in right side. The interface is shown in figure 5.4.10.
Figure 5.4.10
In right box “Other objects”, it can add the file to be linked in the project, click the green plus. The interface is shown in figure 5.4.11. Pay attention to: the linked file path does not contain brackets or special characters. The interface is shown in figure 5.4.12.
Figure 5.4.11
Figure 5.4.12
Click “File system” or “Workspace...”, select the library file to be added, then click “OK”. If the addition is successful, the file path will be displayed. The interface is shown in figure 5.4.13.
Figure 5.4.13
Click the drop-down options of “C/C++ Build” in left side, then select “Settings”, and select “General” under “GNU RISC-V Cross C Create FlashImage” under “Tool Settings” in right side. The interface is shown in figure 5.4.14.
Figure 5.4.14
In right side “output file format (-O)”, click the drop-down options, it can select to generate Intel HEX or Raw binary file. The interface is shown in figure 5.4.15.
Figure 5.4.15
Click the drop-down options of “C/C++ Build” in left side, then select “Build Artifact”. The interface is shown in figure 5.4.16.
Figure 5.4.16
Static library if you want to reduce static library capacity, select “Debugging” under “Tool Setting”, set “Debug level” to NONE.
Artifact name can change the executable file name generated by default, delete the original default name, and write the custom name.
Click the drop-down options of “C/C++ Build” in left side, then select “Settings”, and select “Libraries” under “GNU RISC-V Cross C Linker” under “Tool Settings” in right side. The interface is shown in figure 5.4.17.
Figure 5.4.17
If you change all the above configurations, you must click “Apply” or “Apply and Close” in the corresponding configuration page. Otherwise, the changed configuration is not take effect.
